An integrated circuit (IC) contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information. Within an integrated circuit, metal layers are stacked on top of one another using intermetal or interlayer dielectric layers that insulate the metal layers from each other. Normally, each metal layer must form an electrical contact to at least one additional metal layer. Such electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers, and filling the resulting via with a metal to create an interconnect structure. Metal layers typically occupy etched pathways in the interlayer dielectric. A “via” normally refers to any recessed feature, such as a hole, line or other similar feature, formed within a dielectric layer that provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer. Similarly, recessed features containing metal layers connecting two or more vias are normally referred to as trenches.
A long-recognized objective in the constant advancement of IC technology is the scaling down of IC dimensions. Such scale down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of ICs. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. These advances are driving forces to constantly scale down IC dimensions. An increase in device performance is normally accompanied by a decrease in device area or an increase in device density. An increase in device density requires a decrease in via dimensions used to form interconnects, including a larger aspect ratio (i.e., depth to width ratio). As the minimum feature dimensions on patterned substrates (wafers) steadily decreases, several consequences of this downward scaling are becoming apparent. For example, the recessed features are becoming so small that micro-voids in bulk metal filling of the recessed features are unacceptable. As the width of metal lines is scaled down to smaller submicron and even nanometer dimensions, electromigration failure, which may lead to open and extruded metal lines, is now a well-recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistivity increases substantially, and this increase in line resistivity may adversely affect circuit performance.
The introduction of Cu metal into multilayer metallization schemes for manufacturing integrated circuits is enabled by the damascene Cu plating process and is now extensively used by manufacturers of advanced microprocessors and application-specific circuits. However, Cu metal cannot be put in direct contact with dielectric materials since Cu metal has poor adhesion to the dielectric materials and Cu is known to easily diffuse into common integrated circuit materials such as silicon and dielectric materials where Cu is a mid-bandgap impurity. Furthermore, oxygen can diffuse from an oxygen-containing dielectric material into Cu, thereby decreasing the electrical conductivity of the Cu metal. Therefore, a diffusion barrier material is formed on dielectric materials and other materials in the integrated circuits to surround the Cu metal and prevent diffusion of the Cu into the integrated circuit materials.
A thin film of Ru deposited on a wafer substrate is useful for Cu plating in integrated circuit fabrication. In the past, deposition of Ru on dielectric materials or on diffusion barrier materials has been problematic. The deposition of a thin Ru film by chemical vapor deposition (CVD) or atomic layer deposition (ALD) often resulted in poor morphology of the thin Ru film. The plating of Cu directly onto a thin Ru film has also been problematic in the past. Cu that is plated directly onto a conventional thin Ru film often shows poor adhesion to the thin Ru film, likely due to impurities in the thin Ru film, discontinuous growth of the thin Ru film, and/or the poor morphology/surface roughness of the thin Ru film. As a result, plated Cu deposits unevenly on the substrate and void-free filling of high aspect ratio features is problematic. Furthermore, conventional post Cu plating annealing processes that are performed to attempt to grow large Cu grains in the entire Cu material, and thereby reduce the electrical resistance of the Cu material, are especially problematic for narrow (<100 nm, nm=10−9 m) and high-aspect-ratio recessed features. As the features get smaller the more difficult it is to fill them with large grain Cu. Furthermore, since scaling of future semiconductor devices will continue to ever smaller minimum feature sizes, widths of recessed features will continue to decrease and depths will continue to increase.
There exists a need for depositing high-purity continuous Ru films with low surface roughness that can be integrated with Cu plating of narrow and high-aspect-ratio recessed features to solve the above problems.